With the development of semiconductor IC technologies and after reaching the very deep sub-micron level, the Data Ratio (DR) of the patterns on the mask, i.e., the layout seriously affects the process and fabrication of the wafer. After the technological process is fixed, especially after the etching process is determined, the change of DR will directly affects the change of dimensions and appearance of etched lines, giving rise to the performance failure of components, or even the functional failure thereof. Practical examples in Table 1 show the huge deviations of the Critical Dimension (CD) of the Active arising from the different DR of same.
TABLE 1Different ProductsProduct 1Product 2Product 3DR of a pattern in the 28.20%41.05%42.25%active regionCD Deviation of the−45 nm−35 nm−33 nmactive region
It can be seen that after the parameters of the etching process are solidified, the change of DR will cause the value of CD to change, and will affect the component performance when the CD value deviates to a relatively large extent. That is to say, the value of CD is an important parameter that influences the component performance. Therefore, it is necessary to find methods to confine the DR value to a certain range so that the components can meet relevant performance requirements.
In existing technological processes, only the Fixed Dummy Pattern Filling is adopted to fill dummy patterns so as to meet the DR requirement demanded by relevant technological processes for layers of the Active(Region), the Gate and the Metals, etc., where DRs of patterns on certain layouts need to be corrected. For example, the size of the dummy pattern for the Active is formulated in accordance with the isolation rule and other design rules for technological processes. The dummy pattern is also called the redundant pattern. FIG. 1 illustrates how fixed dummy patterns are filled. Dummy Actives (102) are filled into the empty Passive (Region), i.e., the Field (101). Both the length (d1) and breadth (d2) of the Dummy Active are 4.08 μm and the pitch between every two adjacent Dummy Actives is 2.4 μm. After all the dummy patterns are filled, the DR for partial areas is 40%. However, various kinds of isolation rules must be satisfied while filling dummy patterns. Therefore, some Fields cannot be filled with any dummy patterns. Other layers like the Gate and the Metals, etc. have the same restriction.
The Fixed Dummy Pattern Filling does correct the DR to a certain extent. However, it may not be able to close to the DR as required, or may not be able to overcome the CD deviation arising therefrom due to different layouts and different wiring for different products. Sometimes different etching menus have to be developed in accordance with different DRs with one type of etching process represented by one kind of etching menu, and etching processes need to be changed so as to overcome the CD deviation arising from the DR difference. In this way, the delivery time of products may be directly affected, and it may also give rise to difficulties in managing numerous process menus. Sometimes, it may even bring about huge losses as a result of wrong uses of menus. This problem is particularly noticeable during etching. It may be necessary to deliver different products for the same Metals layer since every approximate difference of 5% may need to correspond with a different etching process.
FIG. 2 illustrates the way fixed dummy patterns are filled under the restriction of isolation rules in accordance with the existing method. There is a Scribe Line Edge (201) on the substrate. The Active region (202) is the area marked with “ACT”; the N-well is (203); the control Gate (204) is the area marked with “GATE”; the dummy pattern is (205); the area marked with (206) is what cannot be filled by dummy patterns. Among all the above, the dummy pattern (205) has a same length and breadth; w1 represents the length or breadth of the dummy pattern (205); w2 represents the minimal pitch between the dummy pattern (205) and the Scribe Line Edge (201); w3 represents the minimal pitch between the dummy pattern (205) and the Active (202); w4 represents the minimal pitch between the dummy pattern (205) and the Gate (204); w5 represents the minimal pitch between the dummy pattern (205) within the N-well (203) and (its adjacent outer edge of) the N-well (203); W6 represents the minimal pitch between the dummy pattern (205) outside the N-well (203) and (its adjacent outer edge of) the N-well (203). Owing to the restriction of w2 and w6, no dummy pattern (205) can be filled into the area (206) since the filling thereof violates the restrictions of w2 and w6.
As shown in FIG. 2, the area (206) where no dummy pattern (205) can be filled is very large. After this area is flattened through a technological process of Chemical and Mechanical Polishing (CMP), a dishing effect will be resulted, bringing about a series of process problems, such as the size reduction of their adjacent Actives, the deformation during the photoetching for the Gate at later stages, etc.